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integrated circuit systems, inc. ics9248-112 0326c?09/18/03 block diagram recommended application: 810/810e type chipset. output features: 2- cpus @2.5v, up to 166.5mhz. 9 - sdram @ 3.3v, up to150mhz including 1 free running 8 - pciclk @ 3.3v 1 - ioapic @ 2.5v, pci or pci/2 mhz 2 - 3v66mhz @ 3.3v, 2x pci mhz 1- 48mhz, @3.3v fixed. 1- 24mhz, @3.3v fixed 1- ref @3.3v, 14.318mhz. features: up to 166mhz frequency support support fs0-fs3 strapping status bit for i 2 c read back. support power management: through power down mode from i 2 c programming. spread spectrum for emi control ( 0.25% center). spread can be enabled or disabled to all 32 frequencies throuth i 2 c. uses external 14.318mhz crystal skew specifications: cpu ? cpu: <175ps sdram - sdram: < 250ps 3v66 ? 3v66: <175ps pci ? pci: <500ps cpu-sdram<500ps for group skew specifications, please refer to group timing relationship table. functionality pin configuration 48-pin 300mil ssop * these inputs have a 120k pull up to vdd. 1. these are double strength. [1:0] frequency generator & integrated buffers for celeron & p ii / iii ? additional frequencies selectable through i 2 c programming. 3 s f2 s f1 s f0 s f u p c ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p ) z h m ( c i p a o i 2 / k l c i c p = 1 ) z h m ( c i p a o i k l c i c p = 0 ) z h m ( 000 0 0 8 . 6 60 2 . 0 0 10 8 . 6 60 4 . 3 30 7 . 6 10 4 . 3 3 000 1 0 0 . 8 60 0 . 2 0 10 0 . 8 60 0 . 4 30 0 . 7 10 0 . 4 3 0010 0 3 . 0 0 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3 001 1 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 13 3 . 4 3 0100 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3 010 1 0 0 . 5 4 15 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 15 2 . 6 3 0110 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3 0111 3 3 . 7 3 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 13 3 . 4 3 100 0 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3 100 1 0 0 . 0 4 10 0 . 0 4 13 3 . 3 97 6 . 6 43 3 . 3 27 6 . 6 4 10 1 0 0 0 . 8 1 10 0 . 8 1 17 6 . 8 73 3 . 9 37 6 . 9 13 3 . 9 3 10 1 1 0 0 . 4 2 10 0 . 4 2 17 6 . 2 83 3 . 1 47 6 . 0 23 3 . 1 4 110 0 0 7 . 3 3 10 7 . 3 3 13 1 . 9 87 5 . 4 48 2 . 2 27 5 . 4 4 110 1 0 0 . 7 3 10 0 . 7 3 13 3 . 1 97 6 . 5 43 8 . 2 27 6 . 5 4 1110 0 0 . 0 5 10 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 10 5 . 7 3 111 1 0 5 . 2 75 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 15 2 . 6 3 vddref
2 ics9248-112 0326c?09/18/03 general description pin configuration power groups gndref, vddref = ref0, x1, x2 gndpci , vddpci = pciclk [9:0] gndsdr, vddsdr = sdram [7:0], sdram_f, supply for pll core gnd3v66 , vdd3v66 = 3v66 gnd48 , vdd48 = 48mhz, 24_48mhz, vddlapic = ioapic gndlcpu , vddlcpu = cpuclk [1:0] the ics9248-112 is a single chip clock solution for designs using the 810/810e style chipset. it provides all necessary clock signals for such a system. spread spectrum may be enabled through i 2 c programming. spread spectrum typically reduces system emi by 8db to 10db. this simplifies emi qualification without resorting to board design iterations or costly shielding. the ics9248- 112 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. serial programming i 2 c interface allows changing functions, stop clock programming and frequency selection. n i p r e b m u n e m a n n i pe p y tn o i t p i r c s e d 11 f e rt u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 , 8 1 , 0 1 , 9 , 2 7 3 , 9 2 , 5 2 d d vr w py l p p u s r e w o p v 3 . 3 31 xn i k c a b d e e f d n a ) f p 3 3 ( p a c d a o l l a n r e t n i s a h , t u p n i l a t s y r c 2 x m o r f r o t s i s e r 42 xt u o d a o l l a n r e t n i s a h . z h m 8 1 3 . 4 1 y l l a n i m o n , t u p t u o l a t s y r c ) f p 3 3 ( p a c , 1 2 , 4 1 , 6 , 5 1 4 , 3 3 , 8 2 d n gr w py l p p u s v 3 . 3 r o f s n i p d n u o r g 8 , 7) 0 : 1 ( 6 6 v 3t u oz h m i c p x 2 t a g n i n n u r b u h r o f s t u p t u o k c o l c v 3 . 3 1 1 0 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 0 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 2 1 1 k l c i c p 1 t u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 1 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l , 6 1 , 5 1 , 3 1 0 2 , 9 1 , 7 1 ) 7 : 2 ( k l c i c pt u os k l c u p c s u o n o r h c n y s h t i w , s t u p t u o k c o l c i c p v 3 . 3 2 2# d pn i e h t n w o d r e w o p o t d e s u n i p t u p n i w o l e v i t c a s u o n o r h c n y s a d e l b a s i d e r a s k c o l c l a n r e t n i e h t . e t a t s r e w o p w o l a o t n i e c i v e d e h t f o y c n e t a l e h t . d e p p o t s e r a l a t s y r c e h t d n a o c v e h t d n a . s m 3 n a h t r e t a e r g e b t o n l l i w n w o d r e w o p 3 2k l c sn ii f o t u p n i k c o l c 2 t u p n i c 4 2a t a d sn ii r o f t u p n i a t a d 2 . t u p n i l a i r e s c 6 2 z h m 8 4t u ob s u r o f t u p t u o k c o l c z h m 8 4 d e x i f v 3 . 3 3 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l 7 2 2 s fn i. n o r e w o p t a d e h c t a l t u p n i . t i b t c e l e s y c n e u q e r f t u p n i c i g o l z h m 4 2t u ot u p t u o z h m 4 2 d e x i f v 3 . 3 0 3f _ m a r d st u oi y b d e t c e f f a t o n m a r d s g n i n n u r e e r f v 3 . 3 2 c , 6 3 , 8 3 , 9 3 , 0 4 1 3 , 2 3 , 4 3 , 5 3 ) 0 : 7 ( m a r d st u os t u p t u o v 3 . 3 2 4l d n gr w pc i p a & u p c r o f y l p p u s r e w o p v 5 . 2 r o f d n u o r g 4 4 , 3 4) 0 : 1 ( k l c u p ct u o. t u p t u o k c o l c s u b t s o h v 5 . 2 7 4 , 5 4l d d vr w pc i p a o i , u p c r o f y l p p u s r e w o p v 5 . 2 6 4c i p a o it u ot u p t u o k c o l c v 5 . 2 8 4 0 f e r 1 t u o. t u p t u o k c o l c e c n e r e f e r z h m 8 1 3 . 4 1 , v 3 . 3 c i p a o i _ q e r fn i k l c i c p = k c o l c c i p a , 0 = c i p a _ q e r f f i ) t l u a f e d ( 2 / k l c i c p = k c o l c c i p a , 1 = c i p a _ q e r f f i 1 double strength
3 ics9248-112 0326c?09/18/03 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d2 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 5 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d3 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 5 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d3 (h) a ck byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack stop bit how to read: controller (host) ics (slave/receiver) start bit address d2 (h) a ck dummy command code a ck dummy byte count a ck byte 0 a ck byte 1 a ck byte 2 a ck byte 3 a ck byte 4 a ck byte 5 a ck stop bit how to write:
4 ics9248-112 0326c?09/18/03 byte0: functionality and frequency select register (default = 0) serial configuration command bitmap note 1 : default at power-up will be for latched logic inputs to define frequency(bit 3 = 0). * these frequencies with spread enabled are equal to original intel defined frequencies with -0.5% down spread. i 2 c is a trademark of philips corporation t i bn o i t p i r c s e dd w p , 2 t i b 4 : 7 t i b ) 4 : 7 , 2 ( t i b k l c u p c ) z h m ( m a r d s ) z h m ( 6 6 v 3 ) z h m ( k l c i c p ) z h m ( c i p a o i _ q e r f ) z h m ( d a e r p s e g a t n e c e r p x x x 1 e t o n 10 00000 0 8 . 6 60 2 . 0 0 10 8 . 6 60 4 . 3 30 7 . 6 10 4 . 3 3r e t n e c % 5 2 . 0 - / + 0000 1 0 0 . 8 60 0 . 2 0 10 0 . 8 60 0 . 4 30 0 . 7 10 0 . 4 3r e t n e c % 5 2 . 0 - / + 000 10 0 3 . 0 0 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3r e t n e c % 5 2 . 0 - / + 000 11 0 0 . 3 0 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 13 3 . 4 3r e t n e c % 5 2 . 0 - / + 00 100 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3r e t n e c % 5 2 . 0 - / + 00 10 1 0 0 . 5 4 15 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 15 2 . 6 3r e t n e c % 5 2 . 0 - / + 00 110 3 7 . 3 3 10 3 . 0 0 17 8 . 6 63 4 . 3 32 7 . 6 13 4 . 3 3r e t n e c % 5 2 . 0 - / + 00 111 3 3 . 7 3 10 0 . 3 0 17 6 . 8 63 3 . 4 37 1 . 7 13 3 . 4 3r e t n e c % 5 2 . 0 - / + 0 1000 0 0 . 0 4 10 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3r e t n e c % 5 2 . 0 - / + 01001 0 0 . 0 4 10 0 . 0 4 13 3 . 3 97 6 . 6 43 3 . 3 27 6 . 6 4r e t n e c % 5 2 . 0 - / + 01010 0 0 . 8 1 10 0 . 8 1 17 6 . 8 73 3 . 9 37 6 . 9 13 3 . 9 3r e t n e c % 5 2 . 0 - / + 01011 0 0 . 4 2 10 0 . 4 2 17 6 . 2 83 3 . 1 47 6 . 0 23 3 . 1 4r e t n e c % 5 2 . 0 - / + 01100 0 7 . 3 3 10 7 . 3 3 13 1 . 9 87 5 . 4 48 2 . 2 27 5 . 4 4r e t n e c % 5 2 . 0 - / + 01101 0 0 . 7 3 10 0 . 7 3 13 3 . 1 97 6 . 5 43 8 . 2 27 6 . 5 4r e t n e c % 5 2 . 0 - / + 0 1110 0 0 . 0 5 10 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 10 5 . 7 3r e t n e c % 5 2 . 0 - / + 0 1111 0 5 . 2 75 7 . 8 0 10 5 . 2 75 2 . 6 33 1 . 8 15 2 . 6 3r e t n e c % 5 2 . 0 - / + 10000 0 0 . 5 70 5 . 2 1 10 0 . 5 70 5 . 7 35 7 . 8 10 5 . 7 3r e t n e c % 5 2 . 0 - / + 1000 1 0 0 . 3 80 0 . 3 87 6 . 7 23 8 . 3 12 9 . 63 8 . 3 1r e t n e c % 5 2 . 0 - / + 10 0 10 0 0 . 0 1 10 0 . 0 1 13 3 . 3 77 6 . 6 33 3 . 8 17 6 . 6 3r e t n e c % 5 2 . 0 - / + 10 0 1 1 0 0 . 0 2 10 0 . 0 2 10 0 . 0 80 0 . 0 40 0 . 0 20 0 . 0 4r e t n e c % 5 2 . 0 - / + 10 10 0 0 0 . 5 2 10 0 . 5 2 13 3 . 3 87 6 . 1 43 8 . 0 27 6 . 1 4r e t n e c % 5 2 . 0 - / + 10 10 1 5 2 . 9 68 8 . 3 0 15 2 . 9 63 6 . 4 31 3 . 7 13 6 . 4 3r e t n e c % 5 2 . 0 - / + 10 1 10 0 0 . 0 70 0 . 5 0 10 0 . 0 70 0 . 5 30 5 . 7 10 0 . 5 3r e t n e c % 5 2 . 0 - / + 10 111 7 6 . 6 70 0 . 5 1 17 6 . 6 73 3 . 8 37 1 . 9 13 3 . 8 3r e t n e c % 5 2 . 0 - / + 11000 0 0 . 5 4 10 0 . 5 4 17 6 . 6 93 3 . 8 47 1 . 4 23 3 . 8 4r e t n e c % 5 2 . 0 - / + 1100 1 0 5 . 6 65 7 . 9 90 5 . 6 65 2 . 3 33 6 . 6 15 2 . 3 3r e t n e c % 5 2 . 0 - / + 110 10 0 0 . 0 5 10 0 . 0 5 10 0 . 0 0 10 0 . 0 50 0 . 5 20 0 . 0 5* r e t n e c % 5 2 . 0 - / + 110 11 5 7 . 9 95 7 . 9 90 5 . 6 65 2 . 3 33 6 . 6 15 2 . 3 3* r e t n e c % 5 2 . 0 - / + 11100 0 0 . 5 5 10 0 . 5 5 13 3 . 3 0 17 6 . 1 53 8 . 5 27 6 . 1 5r e t n e c % 5 2 . 0 - / + 1110 1 0 5 . 6 6 10 5 . 6 6 10 0 . 1 1 10 5 . 5 55 7 . 7 20 5 . 5 5r e t n e c % 5 2 . 0 - / + 11110 3 3 . 3 5 10 0 . 5 1 17 6 . 6 73 3 . 8 37 1 . 9 13 3 . 8 3r e t n e c % 5 2 . 0 - / + 11111 0 0 . 3 3 15 7 . 9 90 5 . 6 65 2 . 3 33 6 . 6 15 2 . 3 3* r e t n e c % 5 2 . 0 - / + 3 t i b s t u p n i d e h c t a l , t c e l e s e r a w d r a h y b d e t c e l e s s i y c n e u q e r f - 0 4 : 7 , 2 t i b y b d e t c e l e s s i y c n e u q e r f - 1 0 1 t i b l a m r o n - 0 d a e r p s r e t n e c % 5 2 . 0 d e l b a n e m u r t c e p s d a e r p s - 1 1 0 t i b g n i n n u r - 0 s t u p t u o l l a e t a t s i r t - 1 0
5 ics9248-112 0326c?09/18/03 byte 1: control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-x# 3 s f 6 t i b-x# 0 s f 5 t i b-x# 2 s f 4 t i b7 21 z h m 4 2 3 t i b-1 ) d e v r e s e r ( 2 t i b6 21 z h m 8 4 1 t i b-1 ) d e v r e s e r ( 0 t i b0 31 f _ m a r d s byte 4: control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) d e v r e s e r ( 6 t i b81 1 _ 6 6 v 3 5 t i b71 0 _ 6 6 v 3 4 t i b-x # c i p a o i _ q e r f 3 t i b6 41 c i p a o i 2 t i b-x# 1 s f 1 t i b3 41 1 k l c u p c 0 t i b4 41 0 k l c u p c byte 3: pci, control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b0 21 7 k l c i c p 6 t i b9 11 6 k l c i c p 5 t i b7 11 5 k l c i c p 4 t i b6 11 4 k l c i c p 3 t i b5 11 3 k l c i c p 2 t i b3 11 2 k l c i c p 1 t i b2 11 1 k l c i c p 0 t i b1 11 0 k l c i c p byte 2: sdram, control register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b1 31 7 m a r d s 6 t i b2 31 6 m a r d s 5 t i b4 31 5 m a r d s 4 t i b5 31 4 m a r d s 3 t i b6 31 3 m a r d s 2 t i b8 31 2 m a r d s 1 t i b9 31 1 m a r d s 0 t i b0 41 0 m a r d s notes: 1. inactive means outputs are held low and are disabled from switching. 2. latched frequency selects (fs#) will be inverted logic load of the input frequency select pin conditions. byte 5: peripheral , active/inactive register (1= enable, 0 = disable) t i b# n i pd w pn o i t p i r c s e d 7 t i b-1 d e v r e s e r 6 t i b-1 d e v r e s e r 5 t i b-1 d e v r e s e r 4 t i b-1 d e v r e s e r 3 t i b-1 d e v r e s e r 2 t i b-1 d e v r e s e r 1 t i b-1 d e v r e s e r 0 t i b-1 d e v r e s e r t i b# n i pd w pn o i t p i r c s e d 7 t i b-0 ) e t o n ( d e v r e s e r 6 t i b-0 ) e t o n ( d e v r e s e r 5 t i b-0 ) e t o n ( d e v r e s e r 4 t i b-0 ) e t o n ( d e v r e s e r 3 t i b-0 ) e t o n ( d e v r e s e r 2 t i b-1 ) e t o n ( d e v r e s e r 1 t i b-1 ) e t o n ( d e v r e s e r 0 t i b-0 ) e t o n ( d e v r e s e r byte 6: peripheral , active/inactive register (1= enable, 0 = disable) note: don?t write into this register. writing into this register can cause malfunction
6 ics9248-112 0326c?09/18/03 fig. 1 shared pin operation - input/output pins the i/o pins designated by (input/output) on the ics9248- 112 serve as dual signal functions to the device. during initial power-up, they act as input pins. the logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. at the end of power-on reset, (see ac characteristics for timing values), the device changes the mode of operation for these pins to an output function. in this mode the pins produce the specified buffered clocks to external loads. to program (load) the internal configuration register for these pins, a resistor is connected to either the vdd (logic 1) power supply or the gnd (logic 0) voltage potential. a 10 kilohm (10k) resistor is used to provide both the solid cmos programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. figure 1 shows a means of implementing this function when a switch or 2 pin header is used. with no jumper installed the pin will be pulled high. with the jumper in place the pin will be pulled low. if programmability is not necessary, then only a single resistor is necessary. the programming resistors should be located close to the series termination resistor to minimize the current loop area. it is more important to locate the series termination resistor close to the driver than the programming resistor.
7 ics9248-112 0326c?09/18/03 pd# timing diagram the power down selection is used to put the part into a very low power state without turning off the power to the part. pd# is an asynchronous active low input. this signal needs to be synchronized internal to the device prior to powering down the clock synthesizer. internal clocks are not running after the device is put in power down. when pd# is active low all clocks need to be driven to a low value and held prior to turning off the vcos and crystal. the power up latency needs to be less than 3 ms. the power down latency should be as short as possible but conforming to the sequence requirements shown below. the ref and 48mhz clocks are expected to be stopped in the low state as soon as possible. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. notes: 1. all timing is referenced to the internal cpuclk (defined as inside the ics9248 device). 2. as shown, the outputs stop low on the next falling edge after pd# goes low. 3. pd# is an asynchronous input and metastable conditions may exist. this signal is synchronized inside this part. 4. the shaded sections on the vco and the crystal signals indicate an active clock. 5. diagrams shown with respect to 133mhz. similar operation when cpu is 100mhz.
8 ics9248-112 0326c?09/18/03 group timing relationship table absolute maximum ratings core supply voltage . . . . . . . . . . . . . . . . . . . . 4.6 v i/o supply voltage . . . . . . . . . . . . . . . . . . . . . 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . . 0c to +70c storage temperature . . . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input/supply/common output parameters t a = 0 - 70c; supply voltage v dd = 3.3 v +/-5%, v ddl = 2.5 v +/-5% (unless otherwise stated) parameter symbol conditions min typ max units input high voltage v ih 2v dd +0.3 v input low voltage v il v ss -0.3 0.8 v input high current i ih v in = v dd -5 5 ma i il1 v in = 0 v; inputs with no pull-up resistors -5 i il2 v in = 0 v; inputs with pull-up resistors -200 i dd3. 3op 300 350 i dd2. 5op 11 15 input frequency f i v dd = 3.3 v 14.312 mhz pin inductance 1 l p in nh c in logic inputs 5 pf c ou t output pin capacitance 6 pf c inx x1 & x2 pins 27 45 pf transition time 1 t trans to 1st crossing of target frequency 3 ms settling time 1 t s from 1st crossing to 1% target frequency 3 ms clk stabilization 1 t stab from v dd = 3.3 v to 1% target frequency 3ms 1 guaranteed by design, not 100% tested in production. 300 i dd3.3pd c l = max loads; with input address to vdd or gnd c l = max loads;select @ 66 mhz operating supply current input capacitance 1 input low current power down supply current 600 ma ma ma group offset tolerance offset tolerance offset tolerance cpu to sdram 2.5ns 500ps 5.0ns 500ps 0.0ns 500ps cpu to 3v66 7.5ns 500ps 5.0ns 500ps 0.0ns 500ps sdram to 3v66 0.0ns 500ps 0.0ns 500ps 0.0ns 500ps 3v66 to pci 1.5-3.5ns 500ps 1.5-3.5ns 500ps 1.5-3.5ns 500ps pci to pci 0.0ns 1.0ns 0.0ns 1.0ns 0.0ns 1.0ns usb & dot async n/a async n/a async n/a cpu 133mhz cpu 66mhz cpu 100mhz
9 ics9248-112 0326c?09/18/03 electrical characteristics - cpu t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp2b v o = v dd *(0.5) 13.5 14 45 w output impedance 1 r dsn2b v o = v dd *(0.5) 12 13 45 w output high voltage v oh2b i oh = -1 ma 2 2.5 v output low voltage v ol2b i ol = 1 ma 0.015 0.4 v v oh @ min = 1.0 v -85 -27 v oh @ max = 2.375 v -27 -9 v ol @ min = 1.2 v 27 68 v ol @ max = 0.3 v 20 30 rise time 1 t r2b v ol = 0.4 v, v oh = 2.0 v 0.4 1.1 1.6 ns fall time 1 t f2b v oh = 2.0 v, v ol = 0.4 v 0.4 1.1 1.6 ns duty cycle 1 d t2b v t = 1.25 v 45 50 55 % skew window 1 t sk2b v t = 1.25 v 50 175 ps v t = 1.25 v; cpu=sdram=100,133 mhz 200 250 cpu=67,133 mhz, sdram=100 mhz 400 500 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc2b ps ma ma output high current output low current i oh2b i ol2b electrical characteristics - 3v66 t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp1b v o = v dd *(0.5) 11 11 55 w output impedance 1 r dsn1b v o = v dd *(0.5) 11 11 55 w output high voltage v oh1 i oh = -1 ma 2.4 3.29 v output low voltage v ol1 i ol = 1 ma 0.009 0.55 v v oh @ min = 1.0 v -136 -33 v oh @ max = 3.135 v -33 -13 v ol @ min = 1.95 v 30 115 v ol @ max = 0.4 v 38 40 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.2 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.3 2 ns duty cycle 1 d t1 v t = 1.5 v 45 53.6 55 % skew window 1 t sk1 v t = 1.5 v 37 175 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 280 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma
10 ics9248-112 0326c?09/18/03 electrical characteristics - ioapic t a = 0 - 70c; v ddl = 2.5 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance r dsp4b 1 v o = v dd *(0.5) 9 1430w output impedance r dsn4b 1 v o = v dd *(0.5) 9 1630w output high voltage v oh4b i oh = -1 ma 2 2.5 v output low voltage v ol4b i ol = 1 ma 0.011 0.4 v v oh @ min = 1.0 v -79 -27 v oh @ max = 2.375 v -27 -10 v ol @ min = 1.2 v 27 66 v ol @ max = 0.3 v 20 30 rise time 1 t r4b v ol = 0.4 v, v oh = 2.0 v 0.4 0.9 1.6 ns fall time 1 t f4b v oh = 2.0 v, v ol = 0.4 v, ioiapic=pci/ 2 0.4 0.9 1.6 ns duty cycle 1 d t4b v t = 1.25 v 455055% jitter, cycle-to-cycle 1 t jcyc-cyc4b v t = 1.25 v 130 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh4b ma output low current i ol4b ma electrical characteristics - sdram t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 20-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp3 v o = v dd *(0.5) 9 9 24 w output impedance 1 r dsn3 v o = v dd *(0.5) 9 9 24 w output high voltage v oh3 i oh = -1 ma 2.4 3.3 v output low voltage v ol3 i ol = 1 ma 0.01 0.4 v v oh @ min = 2.0 v -124 -46 v oh @ max = 3.135 v -54 -20 v ol @ min = 1.0 v 53 105 v ol @ max = 0.4 v 46 54 rise time 1 t r3 v ol = 0.4 v, v oh = 2.4 v 0.5 1 2 ns fall time 1 t f3 v oh = 2.4 v, v ol = 0.4 v 0.5 1 2 ns dut y c y cle 1 d t3 v t = 1.5 v 455355% skew window 1 t sk3 v t = 1.5 v 98 250 ps jitter 1 t j cyc-cyc v t = 1.5 v 170 250 ps 1 guaranteed by design, not 100% tested in production. ma ma output high current output low current i oh3 i ol3
11 ics9248-112 0326c?09/18/03 electrical characteristics - pci t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-30 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp1b v o = v dd *(0.5) 11 11 55 w output impedance 1 r dsn1b v o = v dd *(0.5) 11 11 55 w output high voltage v oh1 i oh = -1 ma 2.4 3.29 v output low voltage v ol1 i ol = 1 ma 0.009 0.55 v v oh @ min = 1.0 v -136 -33 v oh @ max = 3.135 v -33 -13 v ol @ min = 1.95 v 30 115 v ol @ max = 0.4 v 38 40 rise time 1 t r1 v ol = 0.4 v, v oh = 2.4 v 0.5 1.3 2 ns fall time 1 t f1 v oh = 2.4 v, v ol = 0.4 v 0.5 1.6 2 ns duty cycle 1 d t1 v t = 1.5 v 45 51.6 55 % skew window 1 t sk1 v t = 1.5 v 330 500 ps jitter, cycle-to-cycle 1 t jcyc-cyc1 v t = 1.5 v 145 500 ps 1 guaranteed by design, not 100% tested in production. output high current i oh1 ma output low current i ol1 ma electrical characteristics - ref, 48mhz_0 (pin 26) t a = 0 - 70c; v dd = 3.3 v +/-5%; c l = 10-20 pf (unless otherwise specified) parameter symbol conditions min typ max units output impedance 1 r dsp5 v o = v dd *(0.5) 11 11 55 w output impedance 1 r dsn5 v o = v dd *(0.5) 11 11 55 w output high voltage v oh5 i oh = -1 ma 2.4 3.29 v output low voltage v ol5 i ol = 1 ma 0.009 0.55 v v oh @ min = 1.0 v -136 -23 v oh @ max = 3.135 v -29 -13 v ol @ min = 1.95 v 29 115 v ol @ max = 0.4 v 38 40 rise time 1 t r5 v ol = 0.4 v, v oh = 2.4 v 0.5 1.2 4 ns fall time 1 t f5 v oh = 2.4 v, v ol = 0.4 v 0.5 1.2 4 ns duty cycle 1 d t5 v t = 1.5 v 45 53 55 % v t = 1.5 v; 48mhz 200 500 ps v t = 1.5 v; ref 780 1000 ps 1 guaranteed by design, not 100% tested in production. jitter, cycle-to-cycle 1 t jcyc-cyc5 output high current i oh5 ma output low current i ol5 ma
12 ics9248-112 0326c?09/18/03 l o b m y ss n o i s n e m i d n o m m o cs n o i t a i r a vdn . n i m. m o n. x a m. n i m. m o n. x a m a5 9 0 .2 0 1 .0 1 1 .c a0 2 6 .5 2 6 .0 3 6 .8 4 1 a8 0 0 .2 1 0 .6 1 0 . 2 a7 8 0 .0 9 0 .4 9 0 . b8 0 0 .- 5 3 1 0 . c5 0 0 .-0 1 0 . ds n o i t a i r a v e e s e1 9 2 .5 9 2 .9 9 2 . ec s b 5 2 0 . 0 h5 9 3 .-0 2 4 . h0 1 0 .3 1 0 .6 1 0 . l0 2 0 .-0 4 0 . ns n o i t a i r a v e e s 0- 8 48 pin 300 mil ssop package ?for current dimensional specifications, see jedec 95.? .093 dia. pin (optional) d/2 e/2 bottom view a 2 see detail ?a? -e- c end view h pin 1 top view index area parting line l detail ?a? a 1 -e- b a side view -c- -d- seating plane .004 c dimensions in inches ordering information ics9248 y f-112-t designation for tape and reel packaging pattern number (2 or 3 digit number for parts with rom code patterns) package type f=ssop revision designator (will not correlate with datasheet revision) device type (consists of 3 or 4 digit numbers) prefix ics, av = standard device example: ics xxxx y f - ppp - t

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